A known semiconductor memory component is described in the patent specification U.S. Pat. No. 6,546,503.
Commercially conventional semiconductor memory components such as SRAMs, DRAMs and MRAMs are manufactured with regard to the address space and the extent of the smallest addressable memory unit, the data word width. A 512 Mbit DRAM in 32 Mbit×16 organization comprises an address space of 225 bits or 32 Mbits, data words having a length of 16 data bits being addressed in each case. The DRAM then has 16 I/O data line connections and also 225 individually selectable addressing lines. In the simplest case, the addressing lines are selected by means of two binary address decoders each having 13 inputs. The two address decoders are driven via an internal address bus having 13 internal address lines and are loaded successively from an address register. The address register is connected to 13 external address connections of the DRAM via which in each case two address words each having 13 address bits are read successively into the address register.
The semiconductor memory components are provided with surplus, redundant memory cells. Functional memory cells are activated or nonfunctional memory cells are deactivated depending on the result of a functional test of the memory cells, so that an error-free memory cell array of the respectively manufactured size is produced given sufficient resources.
If the functional memory area includes the area which can be completely addressed and evaluated by means of the internal addressing and data lines, then the respective semiconductor memory component is fully functional. The semiconductor memory component is consequently classified as “all good memory” and sorted and treated further as such.
If the redundancy provided in the semiconductor memory component does not suffice to classify a fully functional memory cell array in the above sense, then the respective semiconductor memory component can be configured as such with a restricted memory area. The functional memory area of such a semiconductor memory component is smaller than would be available, that is to say addressable and evaluatable, by means of the internal addressing lines or data lines. A semiconductor memory component having a functional memory area which is smaller than could be made available by means of the addressing lines and data lines is generally classified as “partial good memory” and is consequently sorted and treated further as such.
In the case of a 512 Mbit DRAM classified as a “half good memory,” only half of the memory area available in accordance with the design is functional and either half of the data lines or one of the individual registers of one of the address decoders do not function. Such a half good memory differs from a 256 Mbit DRAM of the same technology which is classified as all good memory by virtue of the total number of memory cells.
A 512 Mbit DRAM downgraded to a half good memory (downgraded DRAM) can functionally replace a 256 Mbit DRAM given corresponding wiring of the address and data line connections.
U.S. Pat. No. 6,810,492 describes memory modules on which in each case a plurality of partial good RDRAMs simulate and replace one or a plurality of fully functional RDRAMs.
U.S. Pat. No. 5,841,957 describes a programmable decoding device for connection of semiconductor memory components having a restricted I/O data area, which are classified as partial good memory, to a standard memory bus.
U.S. Pat. No. 5,668,763 relates to an internal circuit supplementation for DRAMs for increasing the yield of semiconductor memory components which can in each case be classified as partial good memory.
Components classified as partial good memory are used in a multiplicity of applications for which, for instance, the dimensions or the full functionality of the semiconductor memory component are insignificant.
There are obtainable, as partial good memories, half good memories having half the memory capacity of a structurally identical all good memory, “quarter good memories” and “three-quarter good memories” having a quarter and three quarters, respectively, of the original memory area and also audio DRAMs (ADRAMs) for audio applications.
Partial good memories are already identified as such on the unseparated wafer and are subject to the same test cycles as all good memories.
The test cycle for a wafer having semiconductor memory components is illustrated in simplified fashion as a flow diagram in FIG. 1.
A wafer 10 having a multiplicity of semiconductor memory components of identical type, for instance DRAMs, is supplied to a test apparatus for testing the semiconductor memory components. After the beginning of the test 11, defective memory cells are determined in a first memory test 12 (prefuse memory test). It is apparent from the number and localization of the defective memory cells whether a sufficient, at least partial repair of the respective semiconductor memory component is possible. In the course of a repair 13, a functional memory area is in each case configured by blowing fuses in suitable data and addressing lines within the memory cell array and the semiconductor memory component is classified as all good memory or partial good memory. The functional memory area, for the case of an all good memory, corresponds to the maximum available memory area predefined by the internal construction and, for the case of a partial good memory, is a memory area restricted in extent compared with the functional memory area of an all good memory.
The repair 13 is followed by a second memory test 14 (postfuse memory test) on the same or a different test apparatus. During the postfuse memory test, a distinction is initially not made between all good memory and partial good memories. Each semiconductor memory component on the wafer is subjected to the same memory test.
Accordingly, the result of the postfuse memory test 14 is final initially only for the semiconductor memory components classified as all good memories 16 for which no error was ascertained in the entire nominal memory area during the second memory test 14. For semiconductor memory components classified as partial good memory, it is necessary to ascertain, in the course of an evaluation 15, whether the memory cell arrays ascertained during the postfuse memory test 14 were found within the functional memory cell area of the partial good memory or outside the functional memory area of the partial good memory.
The postfuse memory test 14 is carried out in a manner similar to the prefuse memory test 12. A linking of the result of the prefuse memory test 12 with regard to the configuration of the functional memory area of partial good memories with the sequence of the postfuse memory test 14 proves to be not very practicable in the test station for mass production. In order to simplify the sequences in the test station, preferably firstly all of the semiconductor memory components on the same wafer are subjected to the same postfuse memory test 14. In the course of the postfuse memory test 14, a generally compressed pass/fail information item is written to an error data memory (fail memory) of the test apparatus simultaneously for a multiplicity of semiconductor memory components.
Afterward, for semiconductor memory components classified as partial good memory, the error data memory is checked to the effect of whether the defective memory cells identified in the postfuse memory test 14 are within or outside the functional memory area of the partial good memory. If the errors identified are assigned only to the uncoupled, functionless memory area outside the functional memory area, then the respective semiconductor memory component is error free in the context of the classification or sorting as partial good memory.
Usually, on the basis of the prefuse sorting for the semiconductor memory components that are respectively tested in parallel, the error data memories of the test apparatus are partially overwritten successively in the course of the evaluation, an error free information item being entered into the error data memory in each case for the respective nonfunctional memory areas of the semiconductor memory components classified as partial good memory.
If an error is ascertained within the memory area of the partial good memory which is expected to be functional after the repair, then the respective semiconductor memory component is defective.
Such a subsequent evaluation of the defective memory areas of partial good memories is time-consuming. If, on the other hand, the postfuse memory test is dispensed with in order to save time, then all the semiconductor memory components on the semiconductor wafer are rated or classified with lower quality, since a high-quality rating or classification presupposes a test of the memory cells after repair.
Furthermore, higher costs arise since, after the repair, semiconductor memory components that are still defective are initially built up into complete, marketable memory components in a complicated manner before they fail in the final test and are rejected.
For these and other reasons, there is a need for the present invention.